Dactronics Oy
SA/VHDL Method

The SA/VHDL-method has been developed in VTT Electronics and in the University of Oulu. It consists of modelling and verification methods and tools. The modelling method includes a system description language that is a combination of Structured Analysis (SA) and VHDL. The verification method is simulation done by VHDL simulator.

SA/VHDL specification consists of hierarchical data flow diagrams (DFDs) controlled with state transition diagrams (STDs). Typical pair of a data flow and its controlling state transition diagram on lowest hierarchical level is shown on figure 1 and 2.

Figure 1. SA/VHDL Data Flow Diagram

Figure 2. SA/VHDL State Transition Diagram

Data transformations (DTRs, solid bubbles in figure 1) are defined with an one-active-input VHDL processes or with a new DFD. Elements with dashed lines in the figure 1 represent the control of the system.

With SA/VHDL method the system can be specified with four phases. First the essential model of the system must be specified. It is totally implementation independent and is concerned only on essential behaviour of the system. Interfaces to outside world are abstract and show only the logical information flow between system and system's users. Essential model is extended to functional model by specifying system's interfaces as they are or will be implemented. This means that information flow is more accurately defined and some of the DTRs must be refined with new DFDs and some new DTRs must be added to the system's interfaces. DTRs are defined to have performance requirements to satisfy system's port to port timing deadlines. Resource model is derived from functional model by allocating DTRs to different implementation resources. Output delays to DTRs must be specified at this phase. Resource model syntax doesn't allow any use of data in the state transition diagrams. Possible use of variables must be defined with new DTRs. Understanding of the system is easier, because specifications of data and control are efficiently separated on every DFD. It is very visible how separate real-time events affect on individual data transformations. Final implementation models can be constructed by dividing the SA/VHDL architecture to separate SA/VHDL specifications of different resources and parallel hardware.