VHDL Modelling of Microcontrollers and CPU Peripherals
We have experienced with large behavioural models for processor systems and have developed VHDL code generators for modeling large instruction decoders.
VHDL Code Generators and other Design Automation Inhouse Tools
Code generators from graphical and/or textual specifications. With the help of our code generator library we can design and implement VHDL code generators in a very short time. Our rule-based system can handle difficult input semantics and makes accurate error and warning reports. Our code generators accept different ASCII input formats saved with export function on graphical editors/CASE tools or simply created with text editors.
VHDL generators available:
VSYN, reads graphical SA-pictures and generates VHDL structure and templates for RTL synthesis.
BSGEN, reads ASIC pin list and command list for Test Access Port and generates VHDL for synthesis of Boundary Scan (JTAG) test logic of ASIC. Also generates BSDL language for ASIC to be utilized with testing Printed Circuit Board with JTAG.
SYS-RTA+, reads graphical SA-pictures and generates VHDL simulation model of SW/HW partitioned system for Co-Design purposes.